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2nd IEEE International Workshop on Silicon Debug and Diagnosis - SDD05
November 10 - 11, 2005
Austin Convention Center
Austin, Texas, USA
Held in conjunction with ITC and Test Week®

http://evia.ucsd.edu/conferences/sdd/

CALL FOR PAPERS

Scope and Mission -- Author Information -- Committees

Scope and Mission

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Troubleshooting how and why circuits and systems fail is important and is rapidly growing in industry significance. Debug and diagnosis may be needed for yield improvement, process monitoring, debugging the design function, failure mode learning for R&D, or just getting a working first prototype. But the detective work can become tricky. Sources of difficulty include, circuit complexity, packaging, physical access, shortened product creation cycle, the traditional focus on just pass/fail testing and missing tool and equipment capabilities. New and efficient solutions for debug and diagnosis will have a much needed and highly visible impact on productivity. The mission and objective of the SDD05 Workshop is to consider all issues related to debug and diagnosis of circuits and systems - from prototype bring-up to volume production.

The topics of interest include, but are not limited to, the following:

  • Debug Techniques and Methodologies
  • Design/Synthesis for Debug
  • Reuse of DFT for Debug and Diagnosis
  • Diagnosis Methods and Tools
  • Equipment Impact and Techniques
  • Board/System Level Debug & Diagnosis
  • Structured Debug Architectures
  • Microprocessor Debug
  • Debug of Embedded Cores/SoCs
  • System Level Debug
  • Manufacturing & Prototype Environment
  • Impact of Defect Models vs. Fault Models
  • Infrastructure IP for SDD
  • Debug for FPGAs
  • Silicon Debug Tools
  • Silicon Debug Standardization
  • Prototype Turn-on

Author Information

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The workshop objective is to facilitate a valuable interactive information exchange. Both extended abstracts and full papers are acceptable for submission. The length guideline is 3 to 8 pages. Submissions must include a title, keywords, full name and affiliation of all authors and an abstract of roughly 50 words. Clearly describe the idea, value, methods, results, originality, value, and benefits over other methods. Proposals that describe open issues, industry/technology needs or opinions are also welcome. Please identify a primary contact and include their address, phone number, fax number and email address. Submit all submissions (PDF or MS Word format) to the SDD web-site by August 1st, 2005. Authors will be notified of the status of their submissions by September 9th. Final papers are due October 3rd for inclusion in the informal digest of papers. Proposals for discussion panels and other special sessions are also invited. Please include a title, name and contact information of the session organizer, a 1 page abstract, and a list of prospective participants. Please submit these to the web site or contact the Program/Special-Session Chairs.

For general information contact:
Mike Ricchetti - General Chair
ATI Research, Inc.
62 Forest Street
Marlboro, MA 01752-3028
Phone: (508) 486-1118
email: mricchetti@ati.com or mike_ricchetti@ieee.org

For submission information contact:
Fidel Muradali - Program Chair
Phone: (650) 940-1553
email: f_muradali@yahoo.com

Committees

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General Chair
M. Ricchetti - ATI Research, Inc.

Program Chair
F. Muradali

Special Sessions
B. Vermeulen - Philips

Finance
R. Chandramouli - Virage Logic

Local Arrangement Chair
A. Crouch - Inovys

Electronic Media
I. Bayraktaroglu - Sun

Program Committee
M. Abramovici - DAFCA
D. Appello - ST Microelectronics
C. Boit - TU Berlin
D. Burek - Magma
W-T Cheng - Mentor Graphics
B. Cory - nVidia
A. Crouch - Inovys
J. Figueras - U. Barcelona
D. Gizopoulos - U. Piraeus
K. Hatayama - Renesas
Y-C Hsu - Novas
A. Ivanov - UBC
D. Josephson - Intel
R. Kapur - Synopsys
T. McLaurin - ARM
C. Metra - U. Bologna
R. Molyneaux - Sun Microsystems
A. Orailoglu - UCSD
M. Renovell – LIRMM
M.S. Reorda – Poli. Di Torino
G. Roberts - DFT Microsystems
C. Sul - Silicon Image
J. Tyzer - U. Poznan
S. Venkataraman - Intel
B. West - NPTest

Steering Committee
R. Aitken - ARM
F. Muradali
E. J. Marinissen - Philips
M. Ricchetti (Chair) - ATI
T. W. Williams - Synopsys
Y. Zorian - Virage Logic

For more information, visit us on the web at: http://evia.ucsd.edu/conferences/sdd/

The 2nd IEEE International Workshop on Silicon Debug and Diagnosis - SDD05 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society– Test Technology Technical Council

TTTC CHAIR
André IVANOV
University of British Columbia– Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

SENIOR PAST CHAIR
Yervant ZORIAN
Virage Logic– USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


TTTC 2ND VICE CHAIR
Michel RENOVELL
LIRMM– France
Tel. +33 467 418 523
E-mail renovell@lirmm.fr

FINANCE CHAIR
Adit D. SINGH
Auburn University– USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

IEEE DESIGN & TEST EIC
Rajesh K. GUPTA
University of California, Irvine– USA
Tel. +1-949-824-8052
E-mail gupta@uci.edu

TECHNICAL MEETINGS
Cheng-Wen WU

National Tsing Hua Univ.– Taiwan
Tel. +886-3-573-1154
E-mail cww@computer.org

TECHNICAL ACTIVITIES
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica– Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

ASIA & SOUTH PACIFIC
Hideo FUJIWARA
Nara Inst. of Science and Technology– Japan
Tel. +81-74-372-5220
E-mail fujiwara@is.aist-nara.ac.jp

LATIN AMERICA
Marcelo LUBASZEWSKI
Federal Univ. of Rio Grande do Sul (UFRGS)– Brazil
Tel. +34-93-401-6603
E-mail luba@vortex.ufrgs.br

NORTH AMERICA
William R. MANN
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Adit D. SINGH
Auburn University– USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic, Inc.– USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

 

PAST CHAIR
Paolo PRINETTO
Politecnico di Torino– Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 1ST VICE CHAIR
Adit D. SINGH
Auburn University– USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

SECRETARY
Christian LANDRAULT
LIRMM– France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Rob AITKEN
Artisan Components– USA
Tel. +1-408-548-3297
E-mail aitken@artisan.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic, Inc.– USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

Univ. of Piraeus– Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys– USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Joan FIGUERAS
Univ. Politècnica de Catalunya– Spain
Tel. +55-51-228-1633, Ext. 4830
E-mail figueras@eel.upc.es

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut– Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
Michael NICOLAIDIS
iRoC Technologies– Greece
Tel. +33-4-381-20763
E-mail michael.nicolaidis@iroctech.com

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino– Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it


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